Layered semiconductor wafer with low warp and bow, and process for producing it

ABSTRACT

Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 μm, a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

BACKGROUND OF THE INVENTION

1 Field of the Invention

The invention relates to a semiconductor wafer with a diameter of atleast 200 mm produced by a layer transfer process including at least oneRTA step, and comprising a carrier wafer of silicon, an electricallyinsulating layer, and a semiconductor layer located thereon, thesemiconductor wafer having low warp and bow, both in the unprocessedstate and after any desired component fabrication process. Moreover, theinvention relates to a process for producing such wafers.

2. Background Art

SOI (silicon on insulator) wafers are generally produced by transferringa silicon layer from a donor wafer to a carrier wafer, also known as ahandle wafer or a base wafer. Processes for producing SOI wafers bytransferring a silicon layer (layer transfer) are described, forexample, in EP533551A1, WO98/52216A1, and WO03/003430A2. SOI waferscomprise a carrier wafer and a single-crystal silicon covering layer,also known as top layer or device layer, joined thereto. The siliconcovering layer represents what is generally described as the activelayer intended for the fabrication of electronic components. It isjoined to the carrier wafer, which generally also consists ofsingle-crystal silicon, via an electrically insulating intermediatelayer, for example one of silicon oxide. In this context, theintermediate layer may be referred to as a buried oxide layer, or “BOX”.The carrier wafer is usually a polished silicon wafer, generallyobtained from single crystal silicon produced by means of theCzochralski crystal pulling process (CZ process). Wafers of this typeare referred to below as CZ silicon wafers.

The donor wafers used are typically so-called “perfect” or “ultimate”silicon wafers, in order to ensure a low defect density. SOI wafers ofthis type are in particular used as starting material for thefabrication of advanced integrated circuits (advanced ICs), for which inparticular, high switching speeds and low power consumption areimportant. To reduce the surface roughness, it is customary for the SOIwafer to be subjected to a heat treatment, for example an RTA (rapidthermal anneal) treatment. Processes are also known, cf. for exampleEP1158581A1, in which the SOI wafer is subjected firstly to an RTAtreatment and then to a further heat treatment in what is known as abatch furnace. A large number of SOI wafers mounted parallel to oneanother are heat-treated simultaneously in a batch furnace.

However, SOI wafers which are produced by this process have the drawbackof being deformed during this heat treatment, as well as duringsubsequent heat treatments associated with the fabrication of electroniccomponents. This deformation can lead to serious complications in thefabrication of electronic components. For example, duringphotolithography, the SOI wafer which is to be exposed is secured inplace employing a vacuum wafer holder in order to provide a surfacewhich is as planar as possible during exposure. This procedure isintended to ensure that the imaging of the mask pattern on the SOI waferis as accurate as possible. If the wafer is deformed, it cannot becompletely “sucked” onto the vacuum wafer holder, with the result thatthe surface is not planar during exposure. In this case, sharply definedimaging of the mask pattern on the surface is not possible in allregions of the SOI wafer. Moreover, this can lead to a lateral offset inthe mask pattern transferred to the SOI wafer, with the result thatadjacent components overlap and therefore cannot function.

The parameter which best describes the deformation of the SOI wafer andwhich is highly important for the photolithography is the global shape.The global shape of a wafer is described below by the two parameters“warp” and “bow”. The term warp is to be understood as meaning themaximum deviation between any location on the SOI wafer and a planepassing through the center of gravity of the SOI wafer mounted free offorces. An accurate definition of this parameter is to be found instandard ASTM F1390. The term bow is to be understood as meaning themaximum deviation between any location on the SOI wafer mounted free offorces and a plane which is defined by three points on the wafer formingan isosceles triangle. The bow parameter is defined in standard ASTMF534. The bow is generally included in the warp and cannot be greaterthan the warp.

During the fabrication of electronic components comprising theapplication of complicated layer structures with the aid of a largenumber of heat treatment steps, deformation occurs for two reasons,manifesting itself in a deterioration in the warp and bow parameters:firstly, the layer structure of the SOI wafers e.g. silicon carrierwafer, insulating layer of silicon oxide, silicon layer, whichinevitably entails certain stresses, leads to the increased formation ofwarp and bow. SOI wafers produced by the process described aboveadditionally reveal a change in their plastic properties duringcomponent fabrication, which is caused by the formation and growth ofoxygen precipitates (referred to below as BMDs, i.e. bulk microdefects)in the carrier wafer. This change in the plastic properties in turnleads to an increase in warp and bow. This effect is described, albeitfor the significantly simpler case of silicon wafers (i.e. without alayer structure), for example in A. Giannattasio, S. Senkader, S. Azam,R. J. Falster, P. R. Wilshaw: “The Use Of Numerical Simulation ToPredict The Unlocking Stress Of Dislocations In CZ-silicon Wafers, ”MICROELECTRONIC ENGINEERING 70 (2003), pp. 125-130, and K. Jurkschat, S.Senkader, P. R. Wilshaw, D. Gambaro, R. J. Falster: “Onset Of Slip InSilicon Containing Oxide Precipitates, ” J. APPL. PHYS. Vol. 90, No. 7(2001), pp. 3219-3225. Those documents explain the relationship betweeninterstitial oxygen concentration and the slippage mobility: the higherthe interstitial oxygen concentration, the more resistant the siliconwafer becomes to deformation. The interstitial oxygen concentration canthereby be significantly influenced by the oxygen precipitation.

In the text which follows, this additional deformation of the SOI waferin the component fabrication process, which is caused solely by a changein the plastic properties of the SOI wafer, is referred to as DeltaWarpor DeltaBow. To avoid problems in photolithography and associated lossesof yield, both the warp and bow values of the SOI wafer prior tocomponent fabrication and the DeltaWarp and DeltaBow in the componentprocess have to be minimized. However, the prior art RTC processesfailed to produce wafers which have low initial deformation. Duringsubsequent device fabrication, deformation noticeably increases. Itwould thus be desirable to provide an SOI wafer with a low initialdeformation, and one in which subsequent processing does not causesignificant additional deformation in terms of warp and bow.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor wafer with a diameter ofat least 200 mm, comprising a carrier wafer consisting of silicon, anelectrically insulating layer and a semiconductor layer located thereon,the semiconductor wafer having been produced by means of a layertransfer process comprising at least one RTA step, wherein thesemiconductor wafer has a warp of less than 30 μm, a DeltaWarp of lessthan 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm.It is preferable for the carrier wafer of this semiconductor wafer tohave a BMD density in the range from 1·10³/cm² to 1·10⁶/cm², and thusthe present invention also provides a semiconductor wafer having a warpof less than 30 μm and a bow of less than 10 μm, and wherein the carrierwafer has a BMD density in the range from 1·10³/cm² to 1·10⁶/cm².

The present invention further provides a process for producing SOIwafers which meet the above criteria, wherein the layer transfer processinvolves one or more RTA treatments at defined temperature(s) andcooling ramps.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the typical inhomogeneous BMD distribution in an SOI waferproduced by transfer of a silicon layer and heat treatment as describedin EP1158581A1.

FIG. 2 for comparison, shows the different and extensively homogeneousBMD distribution in a conventional, polished CZ silicon wafer.

FIG. 3 shows all the heat treatments which take place during theproduction of the SOI wafer in accordance with EP1158581A1 and thedevelopment of the concentration of the interstititial oxygen, the BMDdensity and the mean BMD radius. The dashed curve 7 denotes thetemperature profile during production of the SOI wafer, the continuouscurve 8 denotes the decimal logarithm of the BMD density.

FIG. 4 shows the variables illustrated in FIG. 3 for the second processaccording to the invention, in which the heat treatment is carried outin two stages. The dashed curve 7 once again denotes the temperatureprofile during the production of the SOI wafer, and the continuous curve8 denotes the decimal logarithm of the BMD density.

FIG. 5 shows the temperature profile of a modern component process asused in the examples.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

On account of its low warp and bow values in the starting state and thelow DeltaWarp and DeltaBow values after the heat treatment in thecomponent process, a semiconductor wafer according to the inventionleads to a significantly wider process window for photolithography andto a significantly higher overall yield in component fabrication. It ispreferable for the warp of the semiconductor wafer according to theinvention to be less than 20 μm and for the bow to be less than 5 μm.Furthermore, the DeltaWarp value of the semiconductor wafer according tothe invention after the fabrication of electronic components ispreferably less than 20 μm. The DeltaBow value is preferably less than 5μm. The BMD density of the carrier wafer of the semiconductor waferaccording to the invention is particularly preferably in the range from1·10³/cm² to 1·10⁵/cm². Moreover, a BMD density which is as homogeneousas possible is preferred, in particular a BMD density which throughoutthe entire volume of the carrier wafer deviates by no more than 50% fromthe mean BMD density throughout the volume of the carrier wafer.

The carrier wafer of the semiconductor wafer according to the inventionpreferably has a specific resistivity in the range from 1 to 1000 Ωcm.

Preferably, the carrier wafer of the semiconductor wafer according tothe invention has an interstitial oxygen concentration in the range from3·10¹⁷/cm³ to 8·10⁷/cm³ and a nitrogen concentration in the range from1·10¹³/cm³ to 5·10¹⁵/cm³. It is particularly preferable to use aninterstitial oxygen concentration in the range from 5·10¹⁷/cm³ to7·10¹⁷/cm³ in combination with a nitrogen concentration in the rangefrom 1·10¹³/cm³ to 5·10¹⁵/cm³, an interstitial oxygen concentration inthe range from 3·10¹⁷/cm³ to 8·10¹⁷/cm³ in combination with a nitrogenconcentration in the range from 5·10¹⁴/cm³ to 5·10¹⁵/cm³ and aninterstitial oxygen concentration in the range from 3·10¹⁷/cm³ to5·10¹⁷/cm³ in combination with a nitrogen concentration in the rangefrom 5·10¹⁴/cm³ to 5·10¹⁵/cm³.

The present invention encompasses all types of semiconductor waferswhich include a carrier wafer made from silicon, an electricallyinsulating layer and any semiconductor layer located thereon, thesewafers having been produced by means of layer transfer with at least oneRTA step. The electrically insulating layer preferably consists ofsilicon oxide, but may also consist of other suitable insulators. Thesemiconductor layer consists of semiconducting material, preferably ofsingle-crystal silicon. In this context, it is only possible to refer toa carrier wafer if the semiconductor wafer is produced by transfer of athin film of silicon from a donor wafer to another wafer, the carrierwafer. SOI wafers which are produced by the known SIMOX process, i.e. byimplantation of oxygen ions and subsequent heat treatment, without alayer being transferred to a carrier wafer, are not carrier wafers inthe sense of the invention and are therefore not within the scope of theinvention.

A semiconductor wafer according to the invention can be produced by theprocesses described below. Each process requires a defined thermaltreatment regimen.

The first process according to the invention comprises a heat treatmentof the semiconductor wafer, in which the semiconductor wafer is heatedat a heating rate of from 10 to 200° C./s until the temperature hasreached a value in the range from 1,100 to 1,250° C., is then held inthis temperature range for a period of 5 s to 300 s, and is then cooledat a cooling rate of from 0.5 to 25° C./s. The cooling rate ispreferably in the range from 0.5 to 15° C.

The second process according to the invention comprises a heat treatmentof the semiconductor wafer, in which the semiconductor wafer is heatedat a heating rate of from 10 to 200° C./s until the temperature hasreached a value in a first range of from 1,100 to 1,250° C., is held inthis first temperature range for a first period of 5 s to 300 s, is thencooled at a first cooling rate of from 10 to 150° C./s until thetemperature is in a second range from 1,000 to 1,150° C., is held in thesecond temperature range for a second period of from 10 s to 300 s, andis subsequently further cooled at a second cooling rate of from 10 to150° C./s.

The third process according to the invention comprises a first heattreatment of the semiconductor wafer, in which the semiconductor waferis heated at a first heating rate of from 10 to 200° C./s until thetemperature has reached a value in a first range of from 1,100 to 1,250°C., is held in this first temperature range for a first period of 5 s to300 s, and is subsequently cooled at a first cooling rate of from 10 to150° C./s, and a second heat treatment of the semiconductor wafer, inwhich the semiconductor wafer is heated at a second heating rate of from10 to 200° C./s until the temperature has reached a value in a secondrange of from 1, 000 to 1,150° C., is then held in the secondtemperature range for a second period of 10 s to 300 s, and issubsequently cooled at a second cooling rate of from 10 to 150° C./s.

In both the second and third inventive processes, the duration of thesecond thermal treatment period is preferably in the range from 30 s to120 s.

The fourth process according to the invention comprises a heat treatmentof the semiconductor wafer under an atmosphere which contains more than12,000 ppm of oxygen, in which the semiconductor wafer is heated at aheating rate of from 10 to 200° C. until the temperature has reached avalue in the range from 1,100 to 1,250° C., is then held in thistemperature range for a period of 5 s to 300 s, and is then cooled at acooling rate of from 10 to 150° C./s.

The atmosphere in the fourth process according to the inventionpreferably contains a noble gas or a mixture of a plurality of noblegases in addition to oxygen. A preferred noble gas is argon. An oxygencontent of at least 20,000 ppm is preferred.

All the processes according to the invention are based on the use of asuitably modified heat treatment, more specifically an RTA treatment aspart of the production of the semiconductor wafer according to theinvention. In the context of the invention, an RTA treatment is to beunderstood as meaning a rapid thermal treatment. The RTA treatment isnot restricted to being carried out in any specific apparatus. By way ofexample, it is possible to use a lamp furnace or an epitaxy reactor oranother suitable apparatus allowing the required high heating andcooling rates. The heat treatment can take place under an atmospherewhich contains one or more of the following gases: nitrogen, oxygen,hydrogen and compounds of these elements with one another, noble gases(e.g. argon), silanes or chlorosilanes. In the fourth process accordingto the invention, however, the atmosphere must include the requiredoxygen content. Moreover, the heat treatment can be carried out undervarious gas pressures, e.g. subatmospheric pressure, atmosphericpressure or superatmospheric pressure. A subsequent heat treatment in abatch furnace as described in EP1158581A 1, is not required.

All the processes according to the invention lead to a reduction in theBMD density and to an unexpected and surprising change in the BMD depthprofile. This altered BMD density and depth profile makes thesemiconductor wafer more resistant to the formation of bow and warp inthermal processes, whether in the process of producing the semiconductorwafer itself or in the subsequent component process.

The four processes according to the invention can also be combined invarious ways.

The inventive change in the heat treatment of the semiconductor wafer,for example an SOI wafer results in significantly reduced values forwarp and bow, both for the semiconductor wafer immediately after it hasbeen produced and also during and after the fabrication of electroniccomponents. DeltaWarp and DeltaBow are therefore likewise considerablyreduced. In particular, the process according to the invention allowsvalues of less than 30 μm, preferably less than 20 μm, to be achievedfor the warp and values of less than 10 μm, preferably less than 5 μm,to be achieved for the bow. Values of less than 30 μm, preferably lessthan 20 μm, are likewise achieved for DeltaWarp, and values of less than10 μm, preferably less than 5 μm, are likewise achieved for DeltaBow.This means that there is only a slight deformation of the wafer duringthe fabrication of electronic components.

A fracture edge analysis of the semiconductor wafers for BMDs (cf.FIG. 1) reveals that the heat treatment according to the invention has asignificant influence on the BMD density of the carrier wafer. With theheat treatment in accordance with EP1158581A1, BMD densities of up tomore than 1·10⁶/cm² are found. Moreover, the BMD density of the carrierwafer is higher by a multiple in the vicinity of the wafer front surface1 than in the vicinity of the wafer back surface 3. By contrast, withthe heat treatment according to the invention, relatively homogeneousBMD densities of less than 1·10⁶/cm², preferably less than 1·10⁵/cm²,are achieved. The BMD density of the semiconductor wafers according tothe invention preferably deviates by no more than 50% from a mean valueformed throughout the entire volume of the carrier wafer.

The reduction in the BMD density has a positive influence on the plasticproperties. This is attributable to an increase in the interstitialoxygen concentration. Moreover, the heat treatment according to theinvention alters the homogeneity of the BMD density, which has abeneficial effect on the layer stress in the SOI wafer. When consideredin combination, the effects lead to the described reduction in bow andwarp, whether immediately after the SOI process or during a heattreatment involved in component fabrication. This allows thephotolithography problems described to be solved.

Another advantage of the invention is that the required changes to theheat treatment of the SOI wafer are simple to implement and have noharmful side effects on other important parameters of the finished SOIwafer.

The prior art has not disclosed a valid model which takes into accountall the variables influencing the mechanical properties, in particularthe deformation resistance of silicon wafers, simultaneously. Thisapplies to an even greater extent in particular to semiconductor waferswith a layer structure which are produced by transferring a siliconlayer and comprise a carrier wafer, an electrically insulating layer anda semiconductor layer.

The SOI wafers referred to have a specific thermal history behind them,leading to a specific BMD formation. FIG. 1 shows a typical BMDdistribution in prior art SOI wafer of this type. The distribution ishighly inhomogeneous, with a relatively low BMD density in the vicinityof the wafer back surface 3 but a BMD density which is higher by amultiple in the vicinity of the wafer front surface 1. The wafer frontsurface bears the thin film of silicon which is intended for thefabrication of electronic components. Overall, the BMD density decreasesfrom the wafer front surface 1 to the center of the wafer 2 and thendecreases further toward the wafer back surface 3. By contrast, thedistribution of the BMD density in a conventional CZ silicon wafer (FIG.2), i.e. a silicon wafer without a layer structure produced from asilicon single crystal pulled using the Czochralski method, isrelatively homogeneous and has a different profile: the BMD densitydecreases from the center of the wafer 5 both toward the wafer frontsurface 4 and toward the wafer back surface 6.

Furthermore, the SOI wafer has a layer structure which leads to layerstresses similar to those in wafers with an epitaxial layer, apolycrystalline silicon layer or a silicon oxide layer.

The combination of the two effects, namely the incorporated layerstresses and the inhomogeneous defect distribution, leads to acomplicated behavior on the part of the global shape, which differssignificantly from the behavior of conventional CZ silicon wafers.

The RTA treatment of the prior art is employed only in order tosufficiently smooth the surface of the transferred silicon layer, whichhas a certain roughness as a result of being separated from theremainder of the donor wafer. According to prior art, this RTA treatmenthas no further objectives (cf. EP1158581A1). It was therefore notobvious to solve the photolithography problem by modifying this RTAtreatment in accordance with the thermal treatment regimens describedherein.

EXAMPLES

In the following Examples and the Comparative Example, a total of ninelayer transfer SOI wafers with a diameter of 300 mm (comprising acarrier wafer of single-crystal silicon, an insulating layer consistingof silicon oxide and a layer of silicon located thereon) were subjectedto different RTA treatments. The BMD density and the warp were measuredafter the RTA treatment. The results are to be found in Table 1 in thecolumns headed “immediately after SOI process”. After thesemeasurements, the SOI wafers were subjected to a heat treatment with atemperature profile typical of the fabrication of modern electroniccomponents. This temperature profile (in °C.) is illustrated as afunction of time (in minutes) in FIG. 5. Warp and BMD density weremeasured once again after this heat treatment. The results are to befound in Table 1 in the columns headed “after component processing”.TABLE 1 immediately after SOI process after component processing BMDdensity Warp BMD density Warp Example [1 · 10⁶/cm²] [μm] [1 · 10⁶/cm²][μm] C 2.03 40.3 2.41 54.7 1A 0.09 15.2 0.09 16.5 1B 0.01 18.1 0.02 19.32A 0.08 14.8 0.09 15.4 2B 0.01 19.5 0.01 21.2 3A 0.01 17.5 0.02 17.9 3B0.03 22.6 0.04 24.7 4A 0.04 21.5 0.04 22.2 4B 0.01 20.9 0.01 21.1

Comparative Example (C): The RTA treatment was carried out in a nitrogenatmosphere in accordance with prior art. The RTA treatment was carriedout in a single stage at a heating rate of 100° C./s to 1,200° C. TheSOI wafer was 15 then held at this temperature for 10 s and then cooledto room temperature at a cooling rate of 100° C./s.

Example 1A

The RTA treatment was carried out in a nitrogen atmosphere in accordancewith the first process according to the invention. The RTA treatment wascarried out in a single stage at a heating rate of 100° C./s to 1,200°C. The SOI wafer was then held at this temperature for 10 s and thencooled to room temperature at a cooling rate of 15° C./s.

Example 1B

The RTA treatment was carried out in a nitrogen atmosphere in accordancewith the first process according to the invention. The RTA treatment wascarried out in a single stage at a heating rate of 100° C./s to 1,200°C. The SOI wafer was then held at this temperature for 10 s and thencooled to room temperature at a cooling rate of 5° C./s.

Example 2A

The RTA treatment was carried out in two stages in a nitrogen atmospherein accordance with the second process according to the invention. TheRTA treatment was carried out at a heating rate of 100° C./s to 1,200°C. The SOI wafer was then held at this temperature for 10 s and thencooled to 1,000° C. at a cooling rate of 100° C./s. The SOI wafer wasthen held at 1,000° C. for 90 s before being cooled to room temperatureat a cooling rate of 100° C./s.

Example 2B

The RTA treatment was carried out in two stages in a nitrogen atmospherein accordance with the second process according to the invention. TheRTA treatment was carried out at a heating rate of 100° C./s to 1,200°C. The SOI wafer was then held at this temperature for 10 s and thencooled to 1,050° C. at a cooling rate of 100° C./s. The SOI wafer wasthen held at 1,050° C. for 240 s before being cooled to room temperatureat a cooling rate of 100° C./s.

Example 3A

The RTA treatment was carried out in two stages in a nitrogen atmospherein accordance with the third process according to the invention. Thefirst stage of the RTA treatment was carried out at a heating rate of100° C./s to 1,200° C. The SOI wafer was then held at this temperaturefor 10 s and then cooled to room temperature at a cooling rate of 100°C./s. The second stage of the RTA treatment was then carried out at aheating rate of 100° C./s to 1,100° C. The SOI wafer was then held atthis temperature for 90 s before being cooled to room temperature at acooling rate of 100° C./s.

Example 3B

The RTA treatment was carried out in two stages in a nitrogen atmospherein accordance with the third process according to the invention. Thefirst stage of the RTA treatment was carried out at a heating rate of100° C./s to 1,200° C. The SOI wafer was then held at this temperaturefor 10 s and then cooled to room temperature at a cooling rate of 100°C./s. The second stage of the RTA treatment was then carried out at aheating rate of 100° C./s to 1,050° C. The SOI wafer was then held atthis temperature for 60 s before being cooled to room temperature at acooling rate of 100° C./s.

Example 4A

The RTA treatment was carried out in a nitrogen atmosphere with anoxygen content of 15,000 ppm in accordance with the fourth processaccording to the invention. The RTA treatment was carried out in asingle stage at a heating rate of 100° C./s to 1,200° C. The SOI waferwas then held at this temperature for 10 s and then cooled to roomtemperature at a cooling rate of 100° C./s.

Example 4B

The RTA treatment was carried out in a nitrogen atmosphere with anoxygen content of 20,000 ppm in accordance with the fourth processaccording to the invention. The RTA treatment was carried out in asingle stage at a heating rate of 100° C./s to 1,200° C. The SOI waferwas then held at this temperature for 10 s and then cooled to roomtemperature at a cooling rate of 100° C./s.

Table 1 shows that the SOI wafers which were heat-treated in accordancewith Examples 1A to 4B have significantly lower BMD densities and warpvalues following this heat treatment than the SOI wafer of theComparative Example. The BMD densities and warp values of the SOI wafersaccording to the invention are also virtually unchanged after thefabrication of electronic components. By contrast, both the BMD densityand the warp increased considerably during component fabrication withthe SOI wafer corresponding to the Comparative Example. The SOI wafersaccording to the invention produced by the process according to theinvention therefore have both significantly lower warp values andDeltaWarp values than SOI wafers in accordance with prior art.

While embodiments of the invention have been illustrated and described,it is not intended that these embodiments illustrate and describe allpossible forms of the invention. Rather, the words used in thespecification are words of description rather than limitation, and it isunderstood that various changes may be made without departing from thespirit and scope of the invention.

1. A semiconductor wafer with a diameter of at least 200 mm, comprisinga silicon carrier wafer, an electrically insulating layer and asemiconductor layer located thereon, the semiconductor wafer having beenproduced by means of a layer transfer process comprising at least oneRTA step, wherein the semiconductor wafer has a warp of less than 30 μm,a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBowof less than 10 μm.
 2. The semiconductor wafer of claim 1, wherein thecarrier wafer has a BMD density in the range from 1·10³/cm² to1·10⁶/cm².
 3. A semiconductor wafer with a diameter of at least 200 mm,comprising a carrier wafer consisting of silicon, an electricallyinsulating layer and a semiconductor layer located thereon, wherein thesemiconductor wafer has a warp of less than 30 μm and a bow of less than10 μm, and wherein the carrier wafer has a BMD density in the range from1·10³/cm² to 1·10⁶/cm².
 4. The semiconductor wafer of claim 1, which hasa warp of less than 20 μm.
 5. The semiconductor wafer of claim 1, whichhas a bow of less than 5 μm.
 6. The semiconductor wafer of claim 1,wherein the carrier wafer has a BMD density in the range from 1·10³/cm²to 1·10⁵/cm².
 7. The semiconductor wafer of claim 1, wherein the carrierwafer has an interstitial oxygen concentration in the range from3·10¹⁷/cm³ to 8·10¹⁷/cm³ and a nitrogen concentration in the range from1·10¹³/cm³ to 5·10¹⁵/cm³.
 8. The semiconductor wafer of claim 7, whereinthe carrier wafer has an interstitial oxygen concentration in the rangefrom 5·10¹⁷/cm³ to 7·10¹⁷/cm³.
 9. The semiconductor wafer of claim 7,wherein the carrier wafer has a nitrogen concentration in the range from5·10¹⁴/cm³ to 5·10¹⁵/cm³.
 10. The semiconductor wafer of claim 9,wherein the carrier wafer has an interstitial oxygen concentration inthe range from 3·10¹⁷/cm³ to 5·10¹⁷/cm³.
 11. The semiconductor wafer ofclaim 1, wherein the BMD density throughout the volume of the carrierwafer deviates by no more than 50% from the mean BMD density throughoutthe entire volume of the carrier wafer.
 12. A process for producing asemiconductor wafer of claim 1, comprising providing a semiconductorwafer with a diameter of at least 200 mm, which comprises a siliconcarrier wafer, an electrically insulating layer and a semiconductorlayer located thereon, and heat treating the semiconductor wafer, inwhich heat treating the semiconductor wafer is heated at a heating rateof from 10 to 200° C./s to a temperature in the range from 1,100 to1,250° C., is held in this temperature range for a period of 5 s to 300s, and is then cooled at a cooling rate of from 0.5 to 25° C./s.
 13. Theprocess of claim 12, in which the cooling rate is from 0.5 to 15° C./s.14. A process for producing a semiconductor wafer of claim 1, comprisingproviding a semiconductor wafer with a diameter of at least 200 mm,which comprises a silicon carrier wafer, an electrically insulatinglayer and a semiconductor layer located thereon, and heat treating thesemiconductor wafer, in which heat treating the semiconductor wafer isheated at a heating rate of from 10 to 200° C./s to a temperature in afirst range from 1,100 to 1,250° C.; is held in the first temperaturerange for a first period of 5 s to 300 s; is then cooled at a firstcooling rate of from 10 to 150° C./s until the temperature is in asecond range of from 1,000 to 1,150° C., the temperature in the secondrange being lower than the temperature in the first range; is then heldin the second temperature range for a second period of 10 s to 300 s;,and is then cooled at a second cooling rate of from 10 to 150° C./s. 15.A process for producing a semiconductor wafer of claim 1, comprisingproviding a semiconductor wafer with a diameter of at least 200 mm,which comprises a silicon carrier wafer, an electrically insulatinglayer and a semiconductor layer located thereon, and subjecting saidsemiconductor wafer to a first heat treatment, in which thesemiconductor wafer is heated at a first heating rate of from 10 to 200°C./s to a temperature in a first range of from 1,100 to 1,250° C., isthen held in the first temperature range for a first period of 5 s to300 s, and is then cooled at a first cooling rate of from 10 to 150°C./s, and a second heat treatment of the semiconductor wafer, in whichthe semiconductor wafer is heated at a second heating rate of from 10 to200° C./s until the temperature has reached a value in a second range offrom 1,000 to 1,150° C., is then held in the second temperature rangefor a second period of 10 s to 300 s, and is then cooled at a secondcooling rate of from 10 to 150° C./s.
 16. The process of claim 14,wherein the duration of the second period is from 30 s to 120 s.
 17. Theprocess of claim 15, wherein the duration of the second period is from30 s to 120 s.
 18. A process for producing a semiconductor wafer ofclaim 1, comprising providing of a semiconductor wafer with a diameterof at least 200 mm, which comprises a silicon carrier wafer, anelectrically insulating layer and a semiconductor layer located thereon,and subjecting said semiconductor wafer to a heat treatment in anatmosphere which contains more than 12,000 ppm of oxygen, in which thesemiconductor wafer is heated at a heating rate of from 10 to 200° C.until the temperature has reached a value in the range from 1,100 to1,250° C., is then held in this temperature range for a period of 5 s to300 s, and is then cooled at a cooling rate of from 10 to 150° C./s. 19.The process as claimed in claim 18, wherein the atmosphere contains atleast 20,000 ppm of oxygen.
 20. A layered semiconductor wafer having adiameter of at least 200 mm, comprising a silicon carrier wafer, asemiconductor layer, and an electrically insulating layer therebetween,wherein said semiconductor wafer is layered as a result of a layertransfer process and is heat treated by minimally one RTA thermaltreatment, said wafer having an interstitial oxygen content of from3·10¹⁷/cm³ to 8·10¹⁷/cm³, a BMD density in the range of 1·10³/cm² to1·10⁶/cm², said BMDs being uniformly distributed throughout the depth ofthe silicon carrier wafer, said semiconductor wafer having a warp ofless than 30 μm, a bow of less than 10 μm, a DeltaWarp of less than 30μm, and a DeltaBow of less than 10 μm.